Data recording method, recording medium and reproduction apparatus

ABSTRACT

A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error correcting codes. The second error correcting codes have the same number of corrections as the first error correcting codes. A code length of the second error correcting codes is shorter than a code length of the first error correcting codes.

This application is a continuation of U.S. patent application Ser. No.11/379,315, filed on Apr. 19, 2006, which is a continuation of U.S.patent application Ser. No. 11/366,140, filed on Mar. 2, 2006, which isa continuation of U.S. patent application Ser. No. 10/484,016, filed onAug. 9, 2004, now U.S. Pat. No. 7,111,222, and similarly claims priorityto International Application No. PCT/JP02/07232, filed Jul. 16, 2002 andJapanese Application No. 2001-220510 filed on Jul. 19, 2001, which arehereby incorporated by reference in their entirety.

TECHNICAL FIELD

The present invention relates to: a data recording method used whendata, such as AV data and computer data, is recorded onto a recordingmedium, such as a DVD; the recording medium storing the data; and anapparatus for reproducing the data from the recording medium.

BACKGROUND ART

Conventionally, an error correcting code, such as a Reed-Solomon Code,has been used to correct errors on a recording medium, such as a DVD,caused by defects of the medium, or dust or scratches attached on thedisk surface.

Recently, in the field of digital video recording, research has beendeveloped toward the next-generation DVDs having higher density andgreater capacity than conventional DVDs. In such research, as thedensity of a recording medium is increased, there is a demand for areduction in the influence of burst errors due to dust or scratches.

To meet such a demand, a recording method has been proposed in, forexample, Kouhei Yamamoto et al., “Error Modeling and PerformanceAnalysis of Error-Correcting Codes for the Digital Video RecordingSystem (Part of the Joint International Symposium on Optical Memory andOptical Data Storage 1999•Koloa, Hi.•July 1999 SPIE Vol. 3864, pp.339-341)”. In this method, two error correcting codes are interleaved soas to improve a capability of correcting burst errors.

Another data recording method, in which two or more error correctingcodes are interleaved, is disclosed in detail in Japanese Laid-OpenPublication No. 2000-40307.

FIG. 9 is a schematic diagram showing a conventional construction oferror correcting codes in Yamamoto et al.

As shown in FIG. 9, user data of about 64 Kbytes is divided into 304columns of 216 bytes each, which are referred to as an informationportion. A parity of 32 bytes is added to each information portion toform a first error correcting code 901. The first error correcting code901 is encoded using Reed-Solomon codes over the finite field GF (256).A component symbol is a minimum element constituting a code and has alength of 1 byte.

The correction capability of the first error correcting code 901 isevaluated as follows.

Generally,d≧2×t+1is established where d represents the minimum distance between each codeand t represents the possible number of corrections.

Each first error correcting code 901 contains a 32-byte parity. Theminimum distance between two first error correcting codes is 33.Therefore, according to the above-described relationship, the firsterror correcting code 901 has correction capability of correcting any upto 16 (byte) errors in the code length of 248 (bytes).

In the correction process, when an error position is known, informationon the known error position can be used to perform erasure correction.Erasure correction is a method in which when a certain code is subjectedto a correction operation and an erroneous component symbol (the minimumunit of a code) is known in advance, the component symbol is assumed tobe erased and the erased component symbol is calculated from theremaining component symbols. When error positions are known, the erasurecorrection can enhance the correction capability by a factor of up to 2.

This can be explained by the following relationship:d≧2×t+e+1,where d represents the minimum distance between each code and trepresent the number of corrections, and e represents the number oferasure corrections.

In the case of the first error correcting code 901 where the minimumdistance d=33, if all corrections are performed by erasure correction(i.e., t=0), up to 32 (bytes) component symbols can be corrected (e=32).

As shown in FIG. 9, control data of 720 bytes is divided into 24 columnsof 30 bytes each, which are referred to as an information portion. Aparity of 32 bytes is added to each information portion to form a seconderror correcting code 902. The second error correcting code 902 isencoded using Reed-Solomon codes over the finite field GF (256). Acomponent symbol is a minimum element constituting a code and has alength of 1 byte. Note that the 720-byte control data contains addressinformation and the like used when the user data is eventually recordedonto an optical disk.

Each second error correcting code 902 also contains a 32-byte parity.The minimum distance between two second error correcting codes 902 is 33as in the first error correcting code 901. Therefore, the second errorcorrecting code 902 has correction capability of correcting any up to 16(byte) errors in the code length of 62 (bytes). The number ofcorrections of the second error correcting code 902 is the same as thatof the first error correcting code 901 (16 (bytes)). However, since thesecond error correcting code 902 has a shorter code length than that ofthe first error correcting code 901, the correction capability of thesecond error correcting code 902 is higher than that of the first errorcorrecting code 901.

In this manner, the first error correcting codes 901 and the seconderror correcting codes 902 are constructed and are then interleavedalong with a synchronization signal 903 to generate data streams whichare in turn recorded onto a recording medium.

FIG. 10 shows a structure of a data stream in which the conventionalfirst error correcting codes 901 and second error correcting codes 902shown in FIG. 9 are interleaved along with a synchronization signalunder a predetermined interleaving rule.

In FIG. 10, 901 a to 901 h indicate first error correcting codes, 902 ato 902 f indicate second error correcting codes, and 903 a and 903 b aresynchronization signals. Component symbols constituting the codes andthe synchronization signals are recorded so that they are arranged in amatrix of 312 columns×248 rows and interleaved in the row direction.Each code is encoded in the column direction (vertical direction) and isto be recorded in a row direction (horizontal direction), therebyproviding the construction which is robust to burst errors. In theconventional example, a synchronization signal of 1 byte is added per155 bytes (=38+1+38+1+38+1+38 bytes). The 156 bytes constitute oneframe. The data stream has a so-called frame structure. Thesynchronization signal is used to synchronize data within a frame on abyte-by-byte basis and specify the position of a frame in the entiredata stream (data block). The synchronization signal is also used topull in synchronization at the start of reproduction or performresynchronization when a bit slip or the like occurs. To this end, thesynchronization signal has a pattern, which cannot be generated bydemodulation performed when a data stream is finally recorded onto anoptical disk, and a predetermined pattern signal comprising a framenumber and the like. The reproduction apparatus determines whether ornot a pattern reproduced by the reproduction apparatus is identical to acorresponding predetermined pattern which should have been recorded,thereby causing the synchronization signal to function.

As is seen from the data construction of FIG. 10, 38 byte componentsymbols in each first error correcting code is interposed between a 1byte synchronization signal and a 1 byte component symbol in a seconderror correcting code or between 1 byte component symbols in two seconderror correcting codes. The ratio of the number of columns having asynchronization signal to the number of columns having component symbolsof a second error correcting code is 1:3. It is possible to generateerasure flags indicating error position information for erasurecorrection, depending on whether or not an error is detected in asynchronization signal or component symbols in a second error correctingcode, based on the result of synchronization detection of asynchronization signal or the result of error correction using a seconderror correcting code having correction capability higher than that ofthe first error correcting codes.

For example, it is assumed that when a second error correcting code issubjected to error correction, an error is detected in component symbolsof two consecutive second error correcting codes 902 e and 902 f (902e-x and 902 f-x in FIG. 10) and error correction is actually performed.In this case, a possibility that an error occurs in 38 byte componentsymbols in the first error correcting code 901 g interposed betweencomponent symbols of the second error correcting codes 902 e-x and 902f-x is considered to be high (i.e., a burst error is assumed to occur).In this case, an erasure flag 905 c is generated for the componentsymbol in the first error correcting code 901 g.

Similarly, for example, for 38 byte component symbols in the first errorcorrecting code 901 a interposed between the synchronization signal 903a and component symbols in the second error correcting code 902 a, and38 byte component symbols in the first error correcting code 901 dinterposed between component symbols in the second error correcting code902 a and the synchronization signal 903 b, an error is detected in theresult of error correction of the second error correcting code or theresult of synchronization detection of whether or not a synchronizationsignal is detected, and using the result, erasure flags are generatedfor component symbols in the first error correcting codes 901 a and 901d. In FIG. 10, an erasure flag 905 a is generated as a result ofdetection of errors in 903 a-x and 902 a-x and an erasure flag 905 b isgenerated as a result of detection of errors in 902 a-x and 903 b-x.

As described above, erasure flags can be used to perform erasurecorrection, thereby making it possible to improve correction capability(the number of corrections) by a factor of up to 2. Therefore, anexcellent resistance to burst errors due to scratches or dust can beobtained.

In the above-described conventional example, the result of errorcorrection of the second error correcting codes or the result ofdetection of a synchronization signal is used to generate acorresponding erasure flag.

The error detection using a second error correcting code is differentfrom the error detection using the synchronization signal in terms ofcapability of detecting errors due to the difference between detectionmethods. The error detection using a synchronization signal hasdetection capability much higher than the error detection using a seconderror correcting code.

In the conventional example, the second error correcting code hascorrection capability higher than that of the first error correctingcode, though the correction capability is as low as 16 (bytes) in 62(bytes). Therefore, when 17 or more (byte) errors occur in 62 (bytes),it is not possible to correct the errors. In this case, it is notpossible to use an erasure flag to specify an error position.

The error detection using a synchronization signal can be performedsimply by comparing a reproduced synchronization signal with thesynchronization signal before reproduction on a bit-by-bit basis. Evenwhen 17 or more (byte) (e.g., 62 byte) errors occur in a synchronizationsignal, all of the errors can be detected.

Therefore, in the conventional example, the same first error correctingcodes have different reliabilities of error correction depending on theposition of the first error correcting code in the data stream, i.e. howthe first error correcting code is interleaved with a second errorcorrecting cods(s) and/or a synchronization signal(s). Specifically, afirst error correcting code interposed between component symbols in twosecond error correcting codes having lower detection capability is lessreliable than another first error correcting code interposed between asynchronization signal and a second error correcting code, due to theerror detection capability.

When higher and lower reliabilities coexist, the reliability of theentirety is constrained by the lowest reliability. In the conventionalexample, it is very likely that an error state, such as incapability ofdata reproduction, occurs in a first error correcting code interposedbetween component symbols in two second error correcting codes havinglower reliability and low error detection capability.

The present invention is provided to solve the above-described problems.The object of the present invention is to provide a data recordingmethod, a recording medium and a reproduction apparatus whose overallcorrection capability is improved by removing the difference in errordetection reliability depending on the position of the first errorcorrecting code in the data stream, i.e., how first error correctingcodes are interleaved with second error correcting codes andsynchronization signals, and by which highly reliable reproduction canbe performed.

DISCLOSURE OF THE INVENTION

The present invention provides a data recording method, comprising thesteps of encoding user data into first error correcting codes having afirst correction capability, encoding control information into seconderror correcting codes having a second correction capability higher thanthe first correction capability, generating a data stream containing thefirst error correcting code, the second error correcting code, andsynchronization signals, in which the second error correcting codes andthe synchronization signals alternatively interleave the first errorcorrecting codes, and recording the data stream. Thereby, theabove-described object can be achieved.

The present invention also provides a recording medium storing a datastream containing first error correcting codes obtained by encoding userdata, second error correcting codes obtained by encoding controlinformation, and synchronization signals, in which the first errorcorrecting codes have a first correction capability, the second errorcorrecting codes have a second correction capability higher than thefirst correction capability, and in the data stream, the second errorcorrecting codes and the synchronization signals alternativelyinterleave the first error correcting codes. Thereby, theabove-described object can be achieved.

The present invention also provides a reproduction apparatus forreproducing the data stream recorded on the recording medium, theapparatus comprising a reproduction section for generating binary datafrom the date stream, a demodulation section for demodulating the binarydata into the first error correcting codes and the second errorcorrecting codes, wherein the demodulation section comprises asynchronization signal detecting section for generating a result ofdetection of the synchronization signal, and an error correcting sectionfor detecting an error in the first error correcting codes and thesecond error correcting codes output from the demodulation section, andcorrecting the error, in which wherein the error correcting sectioncomprises an erasure flag generating section to the first errorcorrecting code for generating an erasure flag for erasure correctionbased on a result of error correction of the second error correctingcode or a result of detection of the synchronization signal, and anerasure correcting section for using the erasure flag to perform erasurecorrection. Thereby, the above-described object can be achieved.

In one embodiment of this invention, when the synchronization signaldetecting section detects the synchronization signal at a time differentfrom a predicted time, the erasure flag generating section places anerasure flag in a component symbol of the first error correcting codeupstream in the data stream from the synchronization signal.

In one embodiment of this invention, when the synchronization signaldetecting section detects the synchronization signal at a time differentfrom a predicted time, and an error is detected in a component symbol ofthe second error correcting code upstream in the data stream from andclosest to the synchronization signal, the erasure flag generatingsection places an erasure flag in a component symbol of the first errorcorrecting code upstream in the data stream from the synchronizationsignal.

In one embodiment of this invention, when the synchronization signaldetecting section detects the synchronization signal at a time differentfrom a predicted time, and an error is not detected in a componentsymbol of the second error correcting code upstream in the data streamfrom and closest to the synchronization signal, the erasure flaggenerating section places an erasure flag in a component symbol of thefirst error correcting code between the second error correcting code andthe synchronization signal.

In one embodiment of this invention, the synchronization signaldetecting section counts the number of clocks and reproduced bits fromthe time of detecting the synchronization signal and, based on thecounting result, predicts a time of detection of the nextsynchronization signal.

The present invention also provides an error correcting circuit for usein the reproduction apparatus, comprising an erasure flag generatingsection to the first error correcting code for generating an erasureflag for erasure correction based on a result of error correction of thesecond error correcting code or a result of detection of thesynchronization signal, and an erasure correcting section for using theerasure flag to perform erasure correction. Thereby, the above-describedobject can be achieved.

In one embodiment of the present invention, when the synchronizationsignal detecting section detects the synchronization signal at a timedifferent from a predicted time, the erasure flag generating sectionplaces an erasure flag in a component symbol of the first errorcorrecting code upstream in the data stream from the synchronizationsignal.

In one embodiment of the present invention, when the synchronizationsignal detecting section detects the synchronization signal at a timedifferent from a predicted time, and an error is detected in a componentsymbol of the second error correcting code upstream in the data streamfrom and closest to the synchronization signal, the erasure flaggenerating section places an erasure flag in a component symbol of thefirst error correcting code upstream in the data stream from thesynchronization signal.

In one embodiment of the present invention, when the synchronizationsignal detecting section detects the synchronization signal at a timedifferent from a predicted time, and an error is not detected in acomponent symbol of the second error correcting code upstream in thedata stream from and closest to the synchronization signal, the erasureflag generating section places an erasure flag in a component symbol ofthe first error correcting code between the second error correcting codeand the synchronization signal.

In one embodiment of the present invention, the synchronization signaldetecting section counts the number of clocks and reproduced bits fromthe time of detecting the synchronization signal and, based on thecounting result, predicts a time of detection of the nextsynchronization signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a structure of a recordingapparatus for recording data into a recording medium according to thepresent invention.

FIG. 2 is a schematic diagram showing first error correcting codes andsecond error correcting codes before being interleaved using a methodaccording to the present invention.

FIG. 3 is a diagram showing a data structure of a data stream in whichfirst error correcting codes and second error correcting codes shown inFIG. 2 are interleaved with synchronization signals in accordance with apredetermined interleaving rule.

FIG. 4 is a diagram showing a structure of data recorded in a spiral orconcentric track of an optical disk according to the present invention.

FIG. 5 is a diagram showing a recording order of a data stream accordingto the present invention.

FIG. 6 is a schematic diagram showing a reproduction apparatus accordingto the present invention.

FIG. 7 is a diagram showing in detail an error correcting circuit shownin FIG. 6.

FIG. 8 is a diagram showing an algorithm for explaining a rule forgenerating an erasure flag.

FIG. 9 is a schematic diagram showing a structure of a conventionalerror correcting code.

FIG. 10 is a diagram showing a data structure of a conventional datastream in which first error correcting codes and second error correctingcodes shown in FIG. 9 are interleaved with synchronization signals inaccordance with a predetermined interleaving rule.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described by way ofillustrative examples with reference to the accompanying drawings.

FIG. 1 is a schematic diagram showing a structure of a recordingapparatus 100 for recording data onto a recording medium. Examples ofthe recording medium include, but are not limited to, optical disks,magnetic disks, and magneto-optic disks. The present invention can beapplied to any recording medium. An optical disk is employed in thefollowing examples.

The recording apparatus 100 comprises an encoder 101, a modulator 102,and a recording circuit 103. The encoder 101 may comprise a firstencoding circuit 104 and a second encoding circuit 105. The modulator102 comprises a modulating circuit 106, a synchronization signalgenerating circuit 107 and an interleaving circuit 108.

User data 109 is input to the first encoding circuit 104. Controlinformation 110 is input to the second encoding circuit 105. The userdata 109 is binary bit data. Examples of the user data 109 include AVdata, text data, and application program data. The control information110 is information used for control of the user data 109. Examples ofthe control information 110 include address information, and copyrightmanagement information (copy permission information, encryption keyinformation, etc.).

The first encoding circuit 104 generates first error correcting codes111 from the user data 109, and sends them to the modulating circuit 106of the modulator 102. Similarly, the second encoding circuit 105generates second error correcting codes 112 from the control information110, and sends them to the modulating circuit 106 of the modulator 102.It is here assumed that the first error correcting code 111 has a firstcorrection capability and the second error correcting code 105 has asecond correction capability higher than the first correctioncapability. The modulating circuit 106 optionally modulates the firsterror correcting code 111 and the second error correcting code 112, andsends the resultant codes to the interleaving circuit 108. Thesynchronization signal generating circuit 107 generates asynchronization signal 115 for correcting bit slips or the like, andsends the synchronization signal 115 to the interleaving circuit 108.The interleaving circuit 108 generates a data stream 116 containing thefirst error correcting codes 111, the second error correcting codes 112and the synchronization signals 115, in which the first error correctingcodes 111 are interleaved alternately with the second error correctingcodes 112 and the synchronization signals 115, and sends the data stream116 to the recording circuit 103. The recording circuit 103 receives thedata stream 116 from the interleaving circuit 108 and records it onto anoptical disk 118 using an optical head 117.

As described, the recording apparatus 100 of the present inventiongenerates a data stream 116 containing the first error correcting codes111, the second error correcting codes 112 and the synchronizationsignals 115, in which the first error correcting codes 111 areinterleaved alternately with the second error correcting codes 112 andthe synchronization signals 115, and records the data stream 116 ontothe optical disk 118.

Next, a data structure along the course of the recording of the userdata 109 and the control information 110 produced by the recordingapparatus 100 of the present invention onto the optical disk 108 will bedescribed with reference to FIGS. 2 to 4.

FIG. 2 is a schematic diagram showing the first error correcting codes111 and the second error correcting codes 112 before being interleaved.

User data of about 64 Kbytes is divided into 304 columns of 216 byteseach, which are referred to as an information portion. A parity of 32bytes is added to each information portion to form a first errorcorrecting code 111. The first error correcting code 111 is encodedusing Reed-Solomon codes over the finite field GF (256). A componentsymbol is a minimum element constituting a code and has a length of 1byte. The encoding direction of the first error correcting code 111 is acolumn direction (vertical direction).

The correction capability of the first error correcting code 111 isevaluated as follows.

Generally,d≧2×t+1is established where d represents the minimum distance between each codeand t represents the possible number of corrections.

Each first error correcting code 111 contains a 32-byte parity. Theminimum distance between two first error correcting codes is 33.Therefore, according to the above-described relationship, the firsterror correcting code 111 has correction capability of correcting any upto 16 (byte) errors in the code length of 248 (bytes).

In the correction process, when an error position is known, informationon the known error position can be used to perform erasure correction.Erasure correction is a method in which when a certain code is subjectedto a correction operation and an erroneous component symbol (the minimumunit of a code) is known in advance, the component symbol is assumed tobe erased and the erased component symbol is calculated from theremaining component symbols. When error positions are known, the erasurecorrection can enhance the correction capability by a factor of up to 2.

This can be explained by the following relationship:d≧2×t+e+1,where d represents the minimum distance between each code and trepresent the number of corrections, and e represents the number oferasure corrections.

In the case of the first error correcting code 111 where the minimumdistance d=33, if all corrections are performed by erasure correction(i.e., t=0), up to 32 (bytes) component symbols can be corrected (e=32).

As shown in FIG. 2, control data of 480 bytes is divided into 16 columnsof 30 bytes each, which are referred to as an information portion. Aparity of 32 bytes is added to each information portion to form a seconderror correcting code 111 z. The second error correcting code 112 isencoded using Reed-Solomon codes over the finite field GP (256). Acomponent symbol is a minimum element constituting a code and has alength of 1 byte. Note that the 480-byte control data contains addressinformation and the like used when the user data is eventually recordedonto an optical disk.

Each second error correcting code 112 also contains a 32-byte parity.The minimum distance between two second error correcting codes 112 is 33as in the first error correcting code 111. Therefore, the second errorcorrecting code 112 has correction capability of correcting any up to 16(byte) errors in the code length of 62 (bytes). The number ofcorrections of the second error correcting code 112 is the same as thatof the first error correcting code 111 (16 (bytes)). However, since thesecond error correcting code 112 has a shorter code length than that ofthe first error correcting code 111, the correction capability of thesecond error correcting code 112 is higher than that of the first errorcorrecting code 111.

In this manner, the first error correcting codes 111 and the seconderror correcting codes 112 are constructed. In the present invention,the recording apparatus 100 alternately interleaves the first errorcorrecting codes 111 with the second error correcting codes 112 and thesynchronization signal 115 to generate the data stream 116 which is inturn recorded onto the optical disk 118.

FIG. 3 shows a structure of the interleaved data stream 116.

In FIG. 3, 111 a to 111 h indicate first error correcting codes, 112 ato 112 d indicate second error correcting codes, and 115 a to 115 dindicate synchronization signals. Component symbols constituting thecodes and the synchronization signals are recorded so that they arearranged in a matrix of 312 columns×248 rows and interleaved in the rowdirection. Each code is encoded in the column direction (verticaldirection) and is to be recorded in the row direction (horizontaldirection), thereby providing the construction which is robust to bursterrors. In this example, a synchronization signal of 1 byte is added per77 bytes (=38+1+38 bytes). The 78 bytes constitute one frame. The datastream has a so-called frame structure. The synchronization signal isused to synchronize data within a frame on a byte-by-byte basis andspecify the position of a frame in the entire data stream (data block).The synchronization signal is also used to pull in synchronization atthe start of reproduction or perform resynchronization when a bit slipor the like occurs. To this end, the synchronization signal has apattern, which cannot be generated by demodulation performed when a datastream is finally recorded onto an optical disk, and a predeterminedpattern signal comprising a frame number and the like. The reproductionapparatus determines whether or not a pattern reproduced by thereproduction apparatus is identical to a corresponding predeterminedpattern which should have been recorded, thereby causing thesynchronization signal to function. Note that although the length of thesynchronization signal is one byte in this example, the length of thesynchronization signal is not necessarily limited to one byte but can beany value depending on the modulation method or the like.

As is seen from the data construction of FIG. 3, 38 byte componentsymbols in each first error correcting code is always interposed betweena 1 byte synchronization signal and a 1 byte component symbol in asecond error correcting code. The ratio of the number of columns havinga synchronization signal to the number of columns having componentsymbols of a second error correcting code is 1:1. It is possible togenerate erasure flags indicating error position information for erasurecorrection, depending on whether or not an error is detected in asynchronization signal or component symbols in a second error correctingcode, based on the result of synchronization detection of asynchronization signal or the result of error correction using a seconderror correcting code having correction capability higher than that ofthe first error correcting codes.

For example, it is assumed that 115 d-x, which is an element of thesynchronization signal 115 d, is not detected and an error is detectedin a component symbol 112 d-x in the second error correcting code 1124in error correction of the second error correcting code 112 d. In thiscase, a possibility that an error occurs in 38 byte component symbols inthe first error correcting code 111 g interposed between 115 d-x and 112d-x is considered to be high (i.e., a burst error is assumed to occur).In this case, an erasure flag 305 b is generated for the componentsymbol in the first error correcting code 111 g.

Similarly, for example, it is assumed that an error is detected in acomponent symbol 112 b-x in the second error correcting code 112 b inerror correction of the second error correcting code 112 b, and 115 o-x,which is an element of the synchronization signal 115 o, in notdetected. In this case, a possibility that an error occurs in 38 bytecomponent symbols in the first error correcting code 111 d interposedbetween 112 b-x and 115 o-x to considered to be high (i.e., a bursterror is assumed to occur). In this case, an erasure flag 305 a isgenerated for the component symbol in the first error correcting code111 d.

As described above, in the present invention, in a data stream, a firsterror correcting code is always interposed between a 1 bytesynchronization signal and a 1 byte component symbol in a second errorcorrecting code. Therefore, all first error correcting codes can besubjected to equal error detection. Therefore, the present invention cancircumvent the above-described conventional problem in which theaccuracy of error detection varies depending on the position of thefirst error correcting code in a data stream, i.e., how the first errorcorrecting code is interleaved with the second error correcting code andthe synchronization signal in the data stream and as a result theoverall reliability of the data stream fluctuates.

As described above, erasure flags can be used to perform erasurecorrection, thereby making it possible to improve correction capability(the number of corrections) by a factor of up to 2. Therefore, anexcellent resistance to burst errors due to scratches or dust an therecording medium surface can be obtained.

When an erasure flag is generated from a synchronization signal, aresynchronization function when a bit slip occurs (an inherent functionof the synchronization signal) can be used to generate an erasure flagwith higher accuracy. For example, in reproduction, when asynchronization signal is detected, however the synchronization signalis reproduced at a position shifted by several clocks from the normalposition, erasure flags are added to only component symbols in a firsterror correcting code recorded upstream along the data stream from thesynchronization signal, rather than resynchronization. This is becausedata upstream along the data stream from a reproduced synchronizationsignal is likely to be erroneous due to loss of synchronization, anddata downstream from the synchronization signal is likely not to beerroneous.

The term “add an erasure flag or generate an erasure flag” refers toattach a mark, which indicates that a component symbol may be erased(i.e., an error may occur in the component symbol), to the componentsymbol. Addition of an erasure flag is performed as follows, forexample. A bit map of 248×304 bits is prepared where one bit is assignedto each symbol of all of the first error correcting codes in a datablock (including 248×304 component symbols). The addition of an erasureflag is represented by causing a corresponding bit to be 1. When noerasure flag is added, a corresponding bit is caused to be 0.

The synchronization signal is herein 1 byte in length, but the lengthmay vary depending on the modulation format or the like.

The first error correcting code and the second error correcting code mayeach contain any number of component symbols.

The error detection using a synchronization signal has an errordetection capability higher than the error detection in which whether ornot an error occurs in each byte is determined. A synchronization signalhaving high detection capability is placed adjacent either before orafter each of all of the first error correcting codes having a unitlength of 38 bytes. Therefore, a highly reliable data recording methodcan be achieved.

As described above, in the data recording method of the presentinvention, the recording apparatus generates a data stream containingfirst error correcting codes, second error correcting codes andsynchronization signals, in which the second error correcting codes andthe synchronization signals alternately interleave the first errorcorrecting codes, and the data stream is recorded onto a recordingmedium. Thus, equal error detection can be applied to all of the firsterror correcting codes. Therefore, the accuracy of error detection doesnot vary depending on the position of the first error correcting code inthe data stream interleaved with the second error correcting code andthe synchronization signals, so that the first error correcting codescan have high reliability throughout the data stream.

FIG. 4 shows data 406 recorded in a spiral or concentric track 402 onthe optical disk 118. The data 406 contains a portion 403 of the firsterror correcting code, a portion 405 of the second error correctingcode, and a portion 404 of the synchronization signal. The data 406 isobtained by dividing the data stream 116 (FIG. 3) into 248 rows alongthe row direction (horizontal direction) and contiguously linking therows. This manner will be described below with reference to FIG. 5.

FIG. 5 is a diagram showing the recording order of the data stream 116.The data stream 116 divided into 248 rows along the row direction, arerecorded onto the optical disk 118 in the order indicated by arrowsshown in FIG. 5. Note that the recording order of the divided datastream 116 is not limited to the manner shown in FIG. 5, but the divideddata stream 116 may be recorded onto the optical disk 118 in any order.

The recording of the optical disk 118 is actually performed with convexand concave pits, variable-density dots of a phase change material, orthe like. In recording, typically, coded data is subjected to digitalmodulation using modulation codes, such as 8/16 modulation or RLL (1,7)codes, before being recorded into a disk track. Note that in FIG. 4, thedescription of the modulation using modulation codes is omitted for thesake of simplicity, and the coded data is recorded as it is.

On the optical disk 118, the data 406 is recorded in the order of aportion 404 of the synchronization signal (1 byte), a portion 403 of thefirst error correcting code (38 bytes), a portion 405 of the seconderror correcting code (1 byte), a portion 403 of the first errorcorrecting code (1 byte), . . . , and so on. In other words, theportions 405 of the second error correcting codes and the portions 404of the synchronization signals alternatively interleave the portions 403of the first error correcting codes.

Thus, in the case of the optical disk of the present invention, data isconstructed so that the component symbols of the second error correctingcodes and the synchronization signals alternately interleave thecomponent symbols of the first error correcting codes, and the data isrecorded onto the optical disk. For this reason, when such an opticaldisk is reproduced, equal error detection can be applied to allcomponent symbols of the first error correcting codes. Therefore, theaccuracy of error detection does not vary depending on the position ofthe first error correcting code in the data stream interleaved with thesecond error correcting code and the synchronization signals, so thatthe first error correcting codes can have high reliability throughoutthe data stream.

Note that the optical disk of the present invention is not limited to anoptical disk recorded using the method of the present invention (i.e.,the method using the recording apparatus 100 shown in FIG. 1), but maybe disks recorded by any method as long as data recorded in the opticaldisk has the above-described data structure.

FIG. 6 is a schematic diagram showing a structure of a reproductionapparatus 600 according to the present invention. The reproductionapparatus 600 reproduces data recorded on the optical disk 118 of thepresent invention. It is here assumed that the data recorded on theoptical disk 118 has the data structure 406 shown in FIG. 4.

The reproduction apparatus 600 comprises a reproduction circuit(reproduction section) 603 for reproducing the data recorded in theoptical disk 118 and generating binary data 611, a demodulation circuit(demodulation section) 604 for demodulating binary data 611 to firsterror correcting codes and second error correcting codes, and an errorcorrecting circuit (error correcting section) 606 for detecting andcorrecting an error in the first error correcting codes and the seconderror correcting codes output by the demodulation circuit 604.

The demodulation circuit 604 comprises a synchronization signaldetection circuit (synchronization signal detecting section) 605 forgenerating a result of detecting a synchronization signal.

The error correcting circuit 606 comprises an erasure flag generatingcircuit (erasure flag generating section) for generating an erasureflag, which is used for erasure correction, to the first errorcorrecting code, based on a result of error correction of the seconderror correcting code or a result of detection of the synchronizationsignal, and an erasure correcting circuit (erasure correcting section)for using the erasure flag to perform erasure correction. These circuitswill be described below. The error correcting circuit 606 detects andcorrects errors on a recording medium due to scratches, dust, or thelike, and generates corrected data 614 from which the errors areremoved.

The reproduction apparatus 600 may further comprise an optical head 117for reading data from the optical disk 118, a WORK RAM 607 for use inthe operation of the error correcting circuit 606, an interface controlcircuit 608 for controlling a protocol, such as SCSI or ATAPI, and acontrol CPU 609. The optical head 117 may comprise a semiconductor laserand an optical element. The interface control circuit 608 performsinterface control for transmitting reproduced user data to a personalcomputer or the like. The control CPU 609 controls the entirereproduction apparatus 600.

In the thus-constructed reproduction apparatus of the present invention,data is reproduced from the optical disk 118 in the following procedure.

Initially, a laser beam is emitted from a semiconductor laser of theoptical head 117 to irradiate the optical disk 118. The laser beam isreflected by the optical disk 118, and the reflected light signal 610 issubjected in the reproduction circuit 603 to conversion to an analogsignal, amplification, and conversion to binary values, and istransmitted as the binary data 611 to the demodulation circuit 604. Thedemodulation circuit 604 digitally demodulates a signal modulated inrecording (digital modulation signal, such as 8/16 modulation or RLL(1,7)). The digitally demodulated data 612 is transmitted to the errorcorrecting circuit 606 in which errors due to scratches, dust, or thelike on a medium are detected and corrected with the help of the WORKRAM 607. Here, the demodulated data 612 contains first error correctingcodes and second error correcting codes. In the demodulation circuit604, the synchronization signal detecting circuit 605 detects asynchronization signal by examining the synchronization signal from thebinary data 611 on a bit-by-bit basis, and performs resynchronization inthe case when data loses synchronization with clocks due to a bit slipor the like. The synchronization signal detecting circuit 605 predictsthe time of detecting a next synchronization signal by counting thenumber of clocks or the number of bytes from a current synchronizationsignal, where the current synchronization signal is present upstream ofthe next synchronization signal along the data stream. When asynchronization signal is detected at a time different from thepredicted time and is subjected to synchronization correction, asynchronization correction signal 613 is transmitted to the errorcorrecting circuit 606. When no synchronization signal is detectedaround the predicted time, a synchronization undetected signal 615 istransmitted to the error correcting circuit 606.

The error correcting circuit 606 decodes the first error correctingcodes and the second error correcting codes. When performing errorcorrection to the first error correcting code, a result of errorcorrection of the second error correcting code, the synchronizationcorrection signal 613, and the synchronization undetected signal 615 areused to generate an erasure flag indicating error position information.The erasure flag is used in erasure correction.

The correction process is employed using known Reed-Solomon codes, forexample. Error-corrected data 614 is transmitted via the interfacecontrol circuit 608 to a host computer or the like (not shown). Theoverall operations for reproduction are controlled by the control CPU609.

FIG. 7 is a diagram specifically showing a structure of the errorcorrecting circuit 606 shown in FIG. 6.

In FIG. 7, the error correcting circuit 606 comprises an erasure flaggenerating circuit (erasure flag generating section) 618 for generatingan erasure flag for erasure correction of the first error correctingcode, based on a result of error correction of the second errorcorrecting code and a result of detection of the synchronization signal,and an erasure correcting circuit (erasure correcting section) 625 forperforming error correction using the erasure flag.

The error correcting circuit 606 may further comprise a bus/memorycontrol circuit 622 for controlling recording and reproduction of theWORK RAM 607 and an internal bus 619, an output IF control circuit 623for outputting the user data 614 after error correction, a first codeerror correcting circuit 624 for decoding the first error correctingcode encoding the user data, and a second code error correcting circuit626 for decoding the second error correcting code containing encodedcontrol information. The output IF control circuit 623 performshandshaking with the interface control circuit 608. The first code errorcorrecting circuit 624 performs error correction to each column of thefirst error correcting code containing 216-byte data and an additional32-byte parity. In error correction, the erasure flag 620 indicating anerror position can be used to perform error correction for up to 32bytes for one code. The erasure correction is performed by the erasurecorrecting circuit 625. The second code error correcting circuit 626corrects the second error correcting code containing 30-byte data and anadditional 32-byte parity, where error correction can be performed on upto 16 bytes for one code. The above-described first code errorcorrecting circuit 624, second code error correcting circuit 626, anderasure correcting circuit 625 can be constructed with an errorcorrecting circuit employing known Reed-Solomon codes or the like.

The error correcting circuit 606 may further comprise an input IFcontrol circuit 616 for performing IF control with the demodulationcircuit 604, and a general control circuit 617 for controlling theentire error correcting circuit 606, which comprises a microcontrolleror the like. The demodulated data 612 input to the input IF controlcircuit 616 is stored via the bus/memory control circuit 622 to the WORKRAM 607. The general control circuit 617 generates the erasure flag 620based on an error position 627 of the second error correcting code fromthe second code error correcting circuit 626, the synchronizationcorrection signal 613, and the synchronization undetected signal 615,and transmits it to the erasure correcting circuit 625.

Next, an operation of the thus-constructed error correcting circuit 606will be described.

The demodulated data 612 reproduced and demodulated from the recordingmedium is stored to the WORK RAM 607 via the input IF control circuit616 and the bus/memory control circuit 622. The first error correctingcode and the second error correcting code of the stored data aredecoded.

For decoding, the second error correcting code is first decoded by thesecond code error correcting circuit 626. The second code errorcorrecting circuit 626 obtains the error position 627 by the decodingand transmits it to the erasure flag generating circuit 618.

The erasure flag generating circuit 618 generates the erasure flag 620based on the synchronization correction signal 613 and thesynchronization undetected signal 615 input at the same time when thedemodulated data 612 is input in advance from the demodulation circuit604 to the input IF control circuit 616, in accordance with apredetermined rule described below, and transmits the erasure flag 620to the erasure correcting circuit 625 of the first code error correctingcircuit 624.

The first code error correcting circuit 624 and the erasure correctingcircuit 625 perform erasure correction to the first error correctingcode based on the erasure flag 620.

After completion of error correction, the user data 614 from whicherrors are removed is transmitted via the output IF control circuit 623to the interface control circuit 608.

The above-described control of the entire error correcting circuit 606or the generation of the erasure flag 620 can be executed by the generalcontrol circuit 617 and the erasure flag generating circuit 618 whichcomprise a microcontroller or the like. The execution can also becarried out by software or a simple logic circuit.

FIG. 8 is a diagram showing an algorithm for explaining a rule forgenerating an erasure flag. In accordance with the generation rule shownin FIG. 8, an erasure flag 420 is generated by software or a simplelogic circuit.

In FIG. 8, a reproduced data sequence is categorized depending on aresult of detection of a synchronization signal or the presence orabsence of an error in the component symbols of a second errorcorrecting code. In FIG. 8, ◯ indicates the normal detection of thesynchronization signal or the absence of an error in component symbolsof the second error correcting code in error correction. X indicatesnon-detection of the synchronization signal, or the presence of an errorin component symbols of the second error correcting code in errorcorrection. Δ indicates that a synchronization signal is detected at atime shifted from the time predicted from the previous synchronizationsignal upstream in the data stream, and synchronization correction iscarried out.

In FIG. 8, 115 e and 115 f indicate synchronization signals, 111 i, 111j and 111 k indicate component symbols of first error correcting codes,and 112 e and 112 f indicates component symbols of second errorcorrecting codes. (A) to the left of FIG. 8 shows a rule for generatingan erasure flag to the component symbol 111 i of the first errorcorrecting code when the synchronization signal 115 e, the componentsymbol 111 i of the first error correcting code, and the componentsymbol 112 e of the second error correcting code are disposed in thisorder. (B) to the right of FIG. 8 shows a rule for generating an erasureflag to the component symbols 111 j and 111 k of the first errorcorrecting code when the component symbol 112 f of the second errorcorrecting code, the component symbol 111 k of the first errorcorrecting code, and the synchronization signal 115 f are disposed inthis order.

[Case of (A) to the Left of FIG. 8]

(a) When the synchronization signal 115 e is normally detected and noerror is detected in the component symbol 112 e of the second errorcorrecting code, no erasure flag is added to the component symbol 111 iof the first error correcting code.

(b) When the synchronization signal 115 e is detected at a time shiftedfrom the time predicted from the previous synchronization signalupstream in the data stream and no error is detected in the componentsymbol 112 e of the second error correcting code, no erasure flag isadded to the component symbol 111 i of the first error correcting code.

(c) When the synchronization signal 115 e is not detected and no erroris detected in the component symbol 112 e of the second error correctingcode is detected, no erasure flag is added to the component symbol 111 iof the first error correcting code.

(d) When the synchronization signal 115 e is normally detected and anerror is detected in the component symbol 112 e of the second errorcorrecting code, no erasure flag is added to the component symbol 111 iof the first error correcting code.

(e) When the synchronization signal 115 e is detected at a time shiftedfrom the time predicted from the previous synchronization signalupstream in the data stream and an error is detected in the componentsymbol 112 e of the second error correcting code, no erasure flag isadded to the component symbol 111 i of the first error correcting code.

(f) When the synchronization signal 115 e is not detected and an erroris detected in the component symbol 112 e of the second error correctingcode is detected, it is assumed that a burst error occurs, and anerasure flag 804 is added to the component symbol 111 i of the firsterror correcting code.

[Case of (B) to the Right of FIG. 8]

(g) When no error is detected in the component symbol 112 f of thesecond error correcting code and the synchronization signal 115 f isnormally detected, no erasure flag is added to the component symbol 111k of the first error correcting code.

(h) When no error is detected in the component symbol 112 f of thesecond error correcting code and the synchronization signal 115 f isdetected at a time shifted from the time predicted from the previoussynchronization signal upstream in the data stream, it is assumed that aburst error occurs due to a bit slip, and an erasure flag 805 is addedto the component symbol 111 k of the first error correcting code.

(i) When no error is detected in the component symbol 112 f of thesecond error correcting code and the synchronization signal 115 f is notdetected, no erasure flag is added to the component symbol 111 k of thefirst error correcting code.

(j) When an error is detected in the component symbol 112 f of thesecond error correcting code and the synchronization signal 115 f isnormally detected, no erasure flag is added to the component symbol 111k of the first error correcting code.

(k) When an error is detected in the component symbol 112 f of thesecond error correcting code and the synchronization signal 115 f isdetected at a time shifted from the time predicted from the previoussynchronization signal upstream in the data stream, it is assumed that aburst error occurs due to a bit slip, and erasure flags 806 and 807 areadded to the component symbols 111 k and 111 j of the first errorcorrecting code.

(l) When an error is detected in the component symbol 112 f of thesecond error correcting code and the synchronization signal 115 f is notdetected, it is assumed that a burst error occurs, and an erasure flags808 is added to the component symbol 111 k of the first error correctingcode.

In accordance with the above-described rules in (A) and (B), erasureflags are generated. The generated erasure flags are used to subject thefirst error correcting code to erasure correction, thereby making itpossible to improve correction capability by a factor of up to 2. Forall of the first error correcting codes, erasure flags are generatedirrespective of the position of the first error correcting code in thedata stream, i.e., how first error correcting codes are interleaved withsecond error correcting codes and synchronization signals, but onlybased on a result of detection of the synchronization signal and aresult of error detection of the component symbols of the second errorcorrecting code.

As described above, in the reproduction apparatus of the presentinvention, erasure flags can be generated for all of the first errorcorrecting codes in an equal manner by error detection of thesynchronization signal and the component symbols of the second errorcorrecting codes. Therefore, the accuracy of error detection does notvary depending on the position of the first error correcting code in thedata stream interleaved with the second error correcting code and thesynchronization signals, so that the first error correcting codes canhave high reliability throughout the data stream.

INDUSTRIAL APPLICABILITY

As described above, in the data recording method, recording medium andreproduction apparatus of the present invention, a data streamcontaining first error correcting codes, second error correcting codesand synchronization signals is generated, in which the second errorcorrecting codes and the synchronization signals alternately interleavethe first error correcting codes, and the data stream is recorded ontothe recording medium by a recording apparatus. Thus, equal errordetection of a burst error can be applied to all of the first errorcorrecting codes. Therefore, the reliability does not vary depending onthe interleaving manner, so that high reliability of error correctioncan be guaranteed throughout the data stream. Thus, with the presentinvention, the data recording method, the optical disk, and thereproduction apparatus each having high reliability can be achieved.

1. A recording medium for storing a data stream containing first errorcorrecting codes obtained by encoding first information, second errorcorrecting codes obtained by encoding second information, andsynchronization signals, wherein: in the data stream, the second errorcorrecting codes and the synchronization signals alternativelyinterleave the first error correcting codes; the second error correctingcodes have the same number of corrections as the first error correctingcodes; a code length of the second error correcting codes is shorterthan a code length of the first error correcting codes; and the secondinformation includes address information.
 2. A reproduction apparatusfor reproducing the data stream recorded on a recording medium accordingto claim
 1. 3. (canceled)